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this is information on a product in full production. october 2014 docid022484 rev 8 1/36 VN7004AH-E high-side driver with currentsense analog feedback for automotive applications datasheet - production data features ? automotive qualified ? general ? single channel smart high-side driver with currentsense analog feedback ? very low standby current ? compatible with 3.0 v and 5 v cmos outputs ? diagnostic functions ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? off-state open-load detection ? output short to v cc detection ? sense enable/ disable ? protections ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? loss of ground and loss of v cc ? reverse battery ? electrostatic discharge protection applications ? all types of automotive resistive, inductive and capacitive loads ? specially intended for automotive headlamps description the VN7004AH-E is a single channel high-side driver manufactured using st proprietary vipower ? technology and housed in the octapak package. the device is designed to drive 12 v automotive grounded loads through a 3 v and 5 v cmos-compatible interface, providing protection and diagnostics. the device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown. a sense enable pin allows off-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. max transient supply voltage v cc 40 v operating voltage range v cc 4 to 28 v typ. on-state resistance (per ch) r on 4.9 m current limitation (typ) i limh 150 a stand-by current (max) i stby 0.5 a ("1($'5 octapak table 1. device summary package order codes tube tape and reel octapak VN7004AH-E vn7004ahtr-e www.st.com
contents VN7004AH-E 2/36 docid022484 rev 8 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 protection against reverse battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 22 4.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 cs - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1 principle of currentsense signal generation . . . . . . . . . . . . . . . . . . . . . 25 4.4.2 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . 27 4.5 maximum demagnetization energy (v cc = 16 v) . . . . . . . . . . . . . . . . . . . 28 5 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 octapak thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 octapak package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid022484 rev 8 3/36 VN7004AH-E list of tables 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. switching (v cc =13v; -40oc list of figures VN7004AH-E 4/36 docid022484 rev 8 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. i out /i sense versus i out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. current sense precision vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. switching times and pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. t dstkon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. i gnd(on) vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. high level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. on-state resistance vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. on-state resistance vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 19. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 20. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. won vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. woff vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. i limh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 24. off-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. v sense clamp vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 26. v senseh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 28. simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 29. currentsense and diagnostic ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 30. currentsense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 31. analogue hsd ? open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 32. open-load / short to vcc condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 33. maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 34. octapak on two-layers pcb (2s0p to jedec jesd 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 35. octapak on four-layers pcb (2s2p to jedec jesd 51-7). . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 36. r thj-amb vs pcb copper area in open box free air conditions . . . . . . . . . . . . . . . . . . . . . . . 30 figure 37. octapak thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 38. thermal fitting model for octapak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 39. octapak package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid022484 rev 8 5/36 VN7004AH-E block diagram and pin description 35 1 block diagram and pin description figure 1. block diagram table 2. pin functions name function v cc battery connection. output power outputs. all the pins must be connected together. gnd ground connection. input voltage controlled input pin with hysteresis. compatible with 3 v and 5 v cmos outputs. it controls output switch state. cs analog current sense output pin delivers a current proportional to the load current. sen active high compatible with 3 v and 5 v cmos outputs pin; it enables the currentsense diagnostic pin. 9 && &rqwuro 'ldjqrvwlf /2*,& '5,9(5 9 21 /lplwdwlrq &xuuhqw /lplwdwlrq 3rzhu &odps 2))6wdwh 2shqordg 2yhu whpshudwxuh 8qghuyrowdjh 9 6(16(+ &xuuhqw 6hqvh 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7,21 ,1 &6 6(q *1' 287 6ljqdo&odps 5hyhuvh %dwwhu\ 3urwhfwlrq ("1($'5
block diagram and pin description VN7004AH-E 6/36 docid022484 rev 8 figure 2. configuration diagram (top view) table 3. suggested connections for unused and not connected pins connection / pin currentsense n.c. output input sen floating not allowed x (1) 1. x: do not care. xxx to ground through 1 k resistor xnot allowed through 15 k resistor through 15 k resistor 065165 065165 065165 */165 $4 4&o (/% 5"#7 $$ ("1($'5
docid022484 rev 8 7/36 VN7004AH-E electrical specification 35 2 electrical specification figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the rating listed in ta ble 4 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in table below for extended periods may affect device reliability. v fn i s i gnd v cc v cc output i out i sense v sense v out cs input sen v in v sen i sen i in note: v f = v out - v cc when v out > v cc and input = low table 4. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 38 v v cc_lsc maximum supply voltage for single pulse short circuit protection (l 5h; r l 100 m ? ) 18 v ccpk maximum transient supply voltage (iso7637-2:2004 pulse 5b level iv clamped to 40 v; r l = 4 ? ) 40 -v cc reverse dc supply voltage 16 -i gnd dc reverse ground pin current 200 ma i out output dc output current internally limited a -i out reverse dc output current 65 i in input dc input current -1 to 10 ma i sen sen dc input current i sense cs pin dc output current (v gnd =v cc and v sense <0v) 10 ma cs pin dc output current in reverse (v cc <0v) -20
electrical specification VN7004AH-E 8/36 docid022484 rev 8 2.2 thermal data e max maximum switching energy (single pulse) t demag = 0.4 ms; i out = 19 a; t jstart = 150c 165 mj v esd electrostatic discharge (jedec 22a-114f) ? input ? currentsense ? sen ? output ?v cc 4000 2000 4000 4000 4000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 table 4. absolute maximum ratings (continued) symbol parameter value unit table 5. thermal data symbol parameter typ. value unit r thj-board thermal resistance junction-board (1) 1. device mounted on four-layers 2s2p pcb 2.1 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-5) (2) 2. device mounted on two-layers 2s0p pcb with 2 cm 2 heatsink copper trace 57.9 r thj-amb thermal resistance junction-ambient (jedec jesd 51-7) (1) 15.4
docid022484 rev 8 9/36 VN7004AH-E electrical specification 35 2.3 electrical characteristics 7v < v cc < 28 v; -40c < t j < 150c, unless otherwise specified. all typical values refer to v cc =13v; t j = 25 c, unless otherwise specified. table 6. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 41328 v v usd undervoltage shutdown 4 v usdreset undervoltage shutdown reset 5 v usdhyst undervoltage shutdown hysteresis 0.3 r on on-state resistance i out =15a; t j =25c 4.9 m i out =15a; t j =150c 9 i out =15a; v cc =4v; t j =25c 6 r on_rev r dson in reverse battery condition v cc =-13v; i out = -15 a; t j =25c 4.9 m v clamp clamp voltage i s = 20 ma; t j = -40c 38 v i s =20ma; 25c electrical specification VN7004AH-E 10/36 docid022484 rev 8 table 7. switching (v cc = 13 v; -40 oc < t j < 150 c, unless otherwise specified) symbol parameter test conditions min. typ. max. unit t d(on) (1) 1. see figure 6: switching times and pulse skew . turn-on delay time at t j =25c r l =0.87 10 70 120 s t d(off) (1) turn-off delay time at t j =25c 10 44 100 (dv out /dt) on (1) turn-on voltage slope at t j =25c r l =0.87 0.1 0.47 0.8 v/s (dv out /dt) off (1) turn-off voltage slope at t j =25c 0.1 0.49 0.8 w on switching energy losses at turn- on (t won ) r l =0.87 ?1.62.7 (2) 2. parameter guaranteed by design and characterization; not subject to production test. mj w off switching energy losses at turn-off (t woff ) r l =0.87 ?1.72.7 (2) mj t skew (1) differential pulse skew (t phl - t plh ) r l =0.87 -30 20 70 s table 8. logic inputs (7 v < v cc < 28 v; -40 c < t j < 150 c) symbol parameter test conditions min. typ. max. unit input characteristics v il input low level voltage 0.9 v i il low level input current v in =0.9v 1 a v ih input high level voltage 2.1 v i ih high level input current v in =2.1v 10 a v i(hyst) input hysteresis voltage 0.2 v v icl input clamp voltage i in =1ma 5.3 7.5 v i in =-1ma -0.7 sen characteristics (7 v < v cc <18v) v senl input low level voltage 0.9 v i senl low level input current v in =0.9v 1 a v senh input high level voltage 2.1 v i senh high level input current v in =2.1v 10 a v sen(hyst) input hysteresis voltage 0.2 v v sencl input clamp voltage i in =1ma 5.3 7.5 v i in =-1ma -0.7
docid022484 rev 8 11/36 VN7004AH-E electrical specification 35 table 9. protections (7 v < v cc < 18 v; -40 c < t j < 150 c) symbol parameter test conditions min. typ. max. unit i limh (1) 1. parameter guaranteed by an indirect test sequence. dc short circuit current v cc =13v; v ds = 5 v 70 150 230 a 4v electrical specification VN7004AH-E 12/36 docid022484 rev 8 i sense 0 currentsense leakage current currentsense disabled: v sen =0v; 00.5a currentsense disabled; -1 v < v sense <5v (1) -0.5 0.5 a currentsense enabled: v sen =5v; v in =5v; i out =0a; 02a v out_csd (1) output voltage for currentsense shutdown v sen =5v; r sense =2.7k ; v in =5v; i out =15a 5v v sense_sat currentsense saturation voltage v cc =7v; r sense =2.7k ? ; v sen =5v; v in =5v; i out =45a; t j =150c 5v i sense_sat (1) cs saturation current v cc =7v; v sense =4v; v in =5v; v sen =5v; t j =150c 4ma i out_sat (1) output saturation current v cc =7v; v sense =4v; v in =5v; v sen =5v; t j =150c 80 a off-state diagnostic v ol off-state open- load voltage detection threshold v in =0v; v sen =5v; 234v i l(off2) off-state output sink current v in =0v; v out =v ol ; t j = -40c to 125c -100 -15 a t dstkon off-state diagnostic delay time from falling edge of input (see figure 7 ) v in = 5 v to 0 v; v sen =5v; i out = 0 a; v out =4v 100 350 700 s t d_ol_v settling time for valid off-state open load diagnostic indication from rising edge of sen v in =0v; v out =4v; v sen = 0 v to 5 v 60 s t d_vol off-state diagnostic delay time from rising edge of v out v in =0v; v sen =5v; v out = 0 v to 4 v 530s fault diagnostic feedback (see table 11 ) v senseh currentsense output voltage in fault condition v cc =13v; v in =0v; v sen =5v; i out = 0 a; v out =4v; r sense =1k 56.6v table 10. currentsense (7 v < v cc <18v; -40c docid022484 rev 8 13/36 VN7004AH-E electrical specification 35 figure 4. i out /i sense versus i out i senseh currentsense output current in fault condition v cc =13v; v sense = 5 v 7 20 30 ma currentsense timings (current sense mode) t dsense1h current sense settling time from rising edge of sen v in =5v; v sen = 0 v to 5 v; r sense =1k ; r l =0.87k 60 s t dsense1l current sense disable delay time from falling edge of sen v in =5v; v sen = 5 v to 0 v; r sense =1k ; r l =0.87k 520s t dsense2h current sense settling time from rising edge of input v in = 0 v to 5 v; v sen =5v; r sense =1k ; r l =0.87k 100 300 s t dsense2h current sense settling time from rising edge of i out (dynamic response to a step change of i out ) v in =5v; v sen =5v; r sense =1k i sense = 90% of i sensemax ; r l =0.87k 200 s t dsense2l current sense turn- off delay time from falling edge of input v in = 5 v to 0 v; v sen =5v; r sense =1k ; r l =0.87k 50 250 s 1. parameter guaranteed by design and characterization; not subject to production test. 2. all values refer to v cc =13v; t j = 25c, unless otherwise specified. table 10. currentsense (7 v < v cc <18v; -40c electrical specification VN7004AH-E 14/36 docid022484 rev 8 figure 5. current sense precision vs. i out figure 6. switching times and pulse skew ("1($'5 ? ? e ? ? ? ? ? ? ?? ? ?? e e? ? 9 / khd ?? ??v??v?vo]????]?]}v ??v??v?o]????]?]}v 9287 w 9ff wzrq 9ff 9ff wzrii ,1387 wgrq ws/+ ws+/ wgrii w g9 287 gw 21 2)) g9 287 gw ("1($'5
docid022484 rev 8 15/36 VN7004AH-E electrical specification 35 figure 7. t dstkon table 11. truth table mode conditions in x sen out x current sense comments stand by all logic inputs low l l l hi-z low quiescent current consumption normal nominal load connected; t j <150c lh l 0 hl h hi-z hh hi sense =1/k*i out overload overload or short to gnd causing: t j >t tsd or t j > t j_sd hl h hi-z output cycles with temperature hysteresis hh h v senseh under- voltage v cc v usd +v usdhys t (rising) off-state diagnostics short to v cc lh h v senseh open-load l h h external pull-up negative output voltage inductive loads turn-off lx<0v 0 7 '67.21 9 ,1387 9 287 0xowl6hqvh 9 287 !9 2/ *$3*&)7
electrical specification VN7004AH-E 16/36 docid022484 rev 8 2.4 electrical characteristics curves figure 8. off-state output current figure 9. standby current figure 10. i gnd(on) vs. i out figure 11. logic input high level voltage figure 12. logic input low level voltage figure 13. high level logic input current 7>?&@ ,orii>q$@ ("1($'5 2ii6wdwh 9ff 9 9lq 9rxw 7>?&@ ,67%<>?$@ 9ff 9 ("1($'5 7>?&@ ,*1'21>p$@ 9ff 9 ,rxw $ ("1($'5 7>?&@ 9l+96(q+>9@ ("1($'5 7>?&@ 9l/96(q/>9@ ("1($'5 7>?&@ ,l+,6(q+>?$@ ("1($'5
docid022484 rev 8 17/36 VN7004AH-E electrical specification 35 figure 14. low level logic input current figure 15. logic input hysteresis voltage figure 16. undervoltage shutdown figure 17. on-state resistance vs. t case figure 18. on-state resistance vs. v cc figure 19. turn-on voltage slope 7>?&@ ,l/,6(q/>?$@ ("1($'5 7>?&@ 9lk\vw96(qk\vw>9@ ("1($'5 7>?&@ 986'>9@ ("1($'5 7>?&@ 5rq>p2kp@ ,rxw $ 9ff 9 ("1($'5 9ff>9@ 5rq>p2kp@ 7 ?& 7 ?& 7 ?& 7 ?& ("1($'5 7>?&@ g9rxwgw2q>9?v@ 9ff 9 5o ("1($'5
electrical specification VN7004AH-E 18/36 docid022484 rev 8 figure 20. turn-off voltage slope figure 21. won vs. t case figure 22. woff vs. t case figure 23. i limh vs. t case figure 24. off-state open-load voltage detection threshold figure 25. v sense clamp vs. t case 7>?&@ g9rxwgw2ii>9?v@ 9ff 9 5o ("1($'5 7>?&@ :rq>p-@ ("1($'5 7>?&@ :rii>p-@ ("1($'5 7>?&@ ,olpk>$@ 9ff 9 ("1($'5 7>?&@ 92/>9@ ("1($'5 7>?&@ 96(16(b&/>9@ ,lq p$ ,lq p$ ("1($'5
docid022484 rev 8 19/36 VN7004AH-E electrical specification 35 figure 26. v senseh vs. t case 7>?&@ 96(16(+>9@ ("1($'5
protections VN7004AH-E 20/36 docid022484 rev 8 3 protections 3.1 power limitation the basic working principle of this protection consists of an indirect measurement of the junction temperature swing t j through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output mosfet as soon as t j exceeds the safety level of t j_sd . the protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 thermal shutdown in case the junction temperature of the device exceeds the maximum allowed threshold (typically 175c), it automatically switches off and the diagnostic indication is triggered. the device switches on again as soon as its junction temperature drops to t r (see ta ble 9 ). 3.3 current limitation the device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, i limh , by operating the output power mosfet in the active region. 3.4 negative voltage clamp in case the device drives inductive load, the output voltage reaches negative value during turn off. a negative voltage clamp structure limits the maximum negative voltage to a certain value, v demag (see tab le 9 ), allowing the inductor energy to be dissipated without damaging the device.
docid022484 rev 8 21/36 VN7004AH-E application information 35 4 application information figure 27. application diagram ("1($'5 9 '' 287 287 $'&lq *1' 5surw 5surw 5vhqvh 5surw &h[w 287 9 /rjlf 287 *1' ,1387 6(q 9 && &6 &xuuhqwpluuru 'og
application information VN7004AH-E 22/36 docid022484 rev 8 4.1 protection against reverse battery figure 28. simplified internal structure the device does not need any external components to protect the internal logic in case of a reverse battery condition. the protection is provided by internal structures. in addition, due to the fact that the output mosfet turns on even in reverse battery mode, thus providing the same low ohmic path as in regular operating conditions, no additional power dissipation has to be considered. 4.2 immunity against transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in accordance with iso7637-2:2011 (e) and iso 16750-2:2010. the related function performance status classification is shown in tab le 12 . test pulses are applied directly to dut (device under test) both in on and off-state and in accordance to iso 7637-2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. status ii is defined in iso 7637-1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. ("1($'5 0&8 ,1387 &6 6(q 9ff 287387 *1' 5surw 5surw 5surw 'og 5vhqvh 9 *1'
docid022484 rev 8 23/36 VN7004AH-E application information 35 4.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line both to prevent the microcontroller i/o pins from latch-up and to protect the hsd inputs. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 1 v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = -150 v; i latchup 20ma; v oh c 4.5v 7.5 k r prot 140 k . recommended values: r prot =15k 4.4 cs - analog current sense diagnostic information on device and load status are provided by an analog output pin (cs) delivering the following signal: ? current monitor: current minitor of channel output current table 12. iso 7637-2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator internal impedance level u s (1) 1. u s is the peak amplitude as defined for each test pulse in iso 7637-2:2011(e), chapter 5.6. min max 1 iii -112v 500 pulses 0,5 s 2ms, 10 2a iii +55v 500 pulses 0,2 s 5 s 50 s, 2 3a iv -220v 1h 90 ms 100 ms 0.1 s, 50 3b iv +150v 1h 90 ms 100 ms 0.1 s, 50 4 (2) 2. test pulse from iso 7637-2:2004(e). iv -7v 1 pulse 100ms, 0.01 load dump according to iso 16750-2:2010 te st b (3) 3. with 40 v external suppressor referred to ground (-40c < t j <150c). 40v 5 pulse 1 min 400ms, 2
application information VN7004AH-E 24/36 docid022484 rev 8 figure 29. currentsense and diagnostic ? block diagram 6(q &xuuhqw6hqvh 5 6(16( 5 3527 7rx&$'& 287 &xuuhqw 6hqvh )dxow )dxow 'ldjqrvwlf 9 6(16(+ , 6(16( , 287 .idfwru *dwh'ulyhu 9&&287 &odps 7 9&&*1' &odps ,qwhuqdo6xsso\ 8qghuyrowdjh vkxwgrzq 921 /lplwdwlrq &xuuhqw /lplwdwlrq 3rzhu/lplwdwlrq 2yhuwhpshudwxuh 6kruwwr9&& 2shq/rdglq2)) &rqwuro 'ldjqrvwlf *1' 9&& ,1387 5hyhuvh %dwwhu\ ("1($'5
docid022484 rev 8 25/36 VN7004AH-E application information 35 4.4.1 principle of currentsense signal generation figure 30. currentsense block diagram current sense this output is capable of providing: ? current mirror proportional to the load current in normal operation , delivering current proportional to the load according to known ratio named k ? diagnostics flag in fault conditions delivering fixed voltage v senseh the current delivered by the current sense circuit, i sense , can be easily converted to a voltage v sense by using an external sense resistor, r sense , allowing continuous load monitoring and abnormal condition detection. normal operation (channel on, no fault, sen active) while device is operating in normal conditions (no fault intervention), v sense calculation can be done using simple equations current provided by currentsense output: i sense = i out /k voltage on r sense : v sense = r sense . i sense = r sense . i out /k ,1387 9ff 287 7rx&$'& 5 3527 5 6(16( 0dlq026 6hqvh026 )dxow &6 &xuuhqwvhqvh6zlwfk%orfn &xuuhqwvhqvh ("1($'5
application information VN7004AH-E 26/36 docid022484 rev 8 where : ? v sense is voltage measurable on r sense resistor ? i sense is current provided from cs pin in current output mode ? i out is current flowing through output ? k factor represents the ratio between powermos cells and sensemos cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between i out and i sense . failure flag indication in case of power limitation/overtemperature, the fault is indicated by the cs pin which is switched to a ?current limited? voltage source, v senseh (see ta ble 10 ). in any case, the current sourced by the cs in this condition is limited to i senseh (see ta ble 10 ). figure 31. analogue hsd ? open-load detection in off-state n n n 9 9edw 5vhqvh n 9 '' 287 287 $'&lq *1' 287 q) *1' *1' *1' *1' *1' *1' q)9 q) q)9 *1' 0lfurfrqwuroohu 287387 9edw n ([whuqdo 3xoo8s vzlwfk /rjlf 287 *1' ,1387 6(q 9 && &6 &xuuhqwpluuru ("1($'5
docid022484 rev 8 27/36 VN7004AH-E application information 35 figure 32. open-load / short to v cc condition 4.4.2 short to v cc and off-state open-load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . table 13. currentsense pin levels in off-state condition output currentsense sen open-load v out >v ol hi-z l v senseh h v out v ol hi-z l v senseh h nominal v out application information VN7004AH-E 28/36 docid022484 rev 8 it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. r pu must be selected in order to ensure v out > v olmax in accordance with the following equation: equation 2 4.5 maximum demagnetization energy (v cc = 16 v) figure 33. maximum turn off current versus inductance 1. values are generated with r l =0 . in case of repetitive pulses, t jstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specif ied above for curves a and b. r pu v pu 4 ? i loff2 () min @ 4v ----------------------------------------- < ("1($'5 ,$ /p+ 91$+ 0d[lpxpwxuqriifxuuhqwyhuvxvlqgxfwdqfh 91$+6lqjoh3xovh 5hshwlwlyhsxovh7mvwduw ?& 5hshwlwlyhsxovh7mvwduw ?&
docid022484 rev 8 29/36 VN7004AH-E package and pcb thermal data 35 5 package and pcb thermal data 5.1 octapak thermal data figure 34. octapak on two-layers pcb (2s0p to jedec jesd 51-5) figure 35. octapak on four-layers pcb (2s2p to jedec jesd 51-7) table 14. pcb properties dimension value board finish thickness 1.6 mm +/- 10% board dimension 77 mm x 86 mm board material fr4 copper thickness (top and bottom layers) 0.070 mm copper thickness (inner layers) 0.035 mm thermal vias separation 1.2 mm thermal via diameter 0.3 mm +/- 0.08 mm copper thickness on vias 0.025 mm footprint dimension (top layer) 6.4 mm x 7mm heatsink copper area dimension (bottom layer) footprint, 2 cm 2 or 8 cm 2 ("1($'5 top gnd plane v cc plane bottom 5pq-bzfs #puupn-bzfs .je-bzfs .je-bzfs ("1($'5
package and pcb thermal data VN7004AH-E 30/36 docid022484 rev 8 figure 36. r thj-amb vs pcb copper area in open box free air conditions figure 37. octapak thermal impeda nce junction ambient single pulse 35)k@bncpo-bzfs1$#?$8 ("1($'5 57+mdpe 57+mdpe ("1($'5 =7+?&: 7lphv &x irrwsulqw &x fp &x fp /d\hu
docid022484 rev 8 31/36 VN7004AH-E package and pcb thermal data 35 equation 3: pulse calculation formula where = t p /t figure 38. thermal fitting model for octapak 1. the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cyc ling during thermal shutdown) are not triggered. table 15. thermal parameters area/island (cm 2 ) footprint 2 8 4l r1 (c/w) 0.005 0.005 0.005 0.005 r2 (c/w) 0.35 0.35 0.35 0.35 r3 (c/w) 1.54 1.54 1.54 1.54 r4 (c/w) 10 10 10 2.5 r5 (c/w) 28 20 12 5 r6 (c/w) 36 26 18 6 c1 (w.s/c) 0.002 0.002 0.002 0.002 c2 (w.s/c) 0.0025 0.0025 0.0025 0.0025 c3 (w.s/c) 0.1 0.1 0.1 0.1 c4 (w.s/c) 0.6 0.6 0.6 0.8 c5 (w.s/c) 0.8 1.4 2.2 3 c6 (w.s/c) 3 6 9 25 z th r th z thtp 1 ? () + ? = ("1($'5
package information VN7004AH-E 32/36 docid022484 rev 8 6 package information 6.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 6.2 octapak package information figure 39. octapak package dimensions ("1($'5
docid022484 rev 8 33/36 VN7004AH-E package information 35 table 16. octapak mechanical data symbol millimeters min. typ. max. a 2.20 2.30 2.40 a1 0.90 1.00 1.10 a2 0.03 0.15 b 0.38 0.45 0.52 b1 0.70 b4 5.20 5.30 5.40 c 0.45 0.50 0.60 c2 0.75 0.80 0.90 d 6.00 6.10 6.20 d1 5.15 e 6.40 6.50 6.60 e1 5.30 e 0.85 bsc e1 1.60 1.70 1.80 e2 3.30 3.40 3.50 e3 5.00 5.10 5.20 h 9.35 9.70 10.10 l1.00 (l1) 2.80 l2 0.80 l3 0.85 r 0.40 bsc v2 0 8
revision history VN7004AH-E 34/36 docid022484 rev 8 7 revision history table 17. document revision history date revision changes 26-jul-2012 1 initial release 20-mar-2013 2 updated features list table 2: pin functions : ? gnd, input, sen: updated functions updated table 3: suggested connections for unused and not connected pins table 4: absolute maximum ratings : ?v cc , -i out : updated value ?v ccjs : added row ?v ccpk , i sense , v esd : updated parameter and value ?-v sense : removed row table 5: thermal data : ?r thj-case : removed row ?r thj-board : added row table 6: power section : ?v usdreset , r on_rev , i gnd(on) : added row ?v clamp : added test conditions and value ?i stby , i l(off) : updated parameter definition ?i s(on) : updated values updated table 7: switching (v cc =13v; -40oc docid022484 rev 8 35/36 VN7004AH-E revision history 35 27-mar-2014 4 updated features list. updated figure 2: configuration diagram (top view) table 4: absolute maximum ratings : ?e max : updated parameter and value updated table 5: thermal data table 6: power section : ?r on , r on_rev : updated values table 7: switching (v cc =13v; -40oc VN7004AH-E 36/36 docid022484 rev 8 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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